The present invention relates to an electrically programmable nonvolatile semiconductor memory device and, more particularly, to a technology which is effective if applied to a flash memory equipped with a word driver for feeding a positive voltage in a program mode and a negative voltage in an erase mode.
A flash memory to be used as an electrically programmable nonvolatile semiconductor memory device can be electrically programmed like an EEPROM (i.e., Electrically Erasable and Programmable Read Only Memory) composed of memory cells as MNOS (i.e., Metal Nitride Oxide Semiconductor). Moreover, one memory cell is constructed of one element like an EPROM (i.e., Erasable and Programmable Read Only Memory) composed of an FAMOS (i.e., Floating gate Avalanche injection Metal Oxide Semiconductor) as its memory cell. The memory cell for such flash memory has the floating gate field effect transistor structure like the FAMOS type, and the programming is carried out by injecting hot electrons generated in the vicinity of the drain junction into the floating gate, and the erasure is carried out by establishing a high electric field between the floating gate and the source and by making use of the tunnel phenomenon through the thin gate oxide film to extract the electrons stored in the floating gate to the source. By the programming operation, the memory cell is given a higher threshold voltage, as viewed from its control gate, than that of the memory cell which is left in the erasing state because it is not programmed. In either the programming or erasing state, the memory transistor has its threshold voltage set to a positive voltage level. Specifically, the threshold voltage in the programming state is higher whereas the threshold voltage in the erasing state is lower than the word line selecting level which is fed from the word line to the control gate. Thanks to this relation between both the threshold voltage and the word line selecting level, a memory cell can be constructed of one transistor without adopting any select transistor.
The technology using a negative voltage is disclosed as one for erasing the aforementioned flash memory in Japanese Patent Laid-Open No. 219496/1991. According to this disclosure, when a batch erasing operation is to be effected in the nonvolatile semi-conductor memory device such as the flash memory, the voltage to be applied to the source region (or the drain region) of each memory cell is fed from the Vcc power source (i.e., the power source at 5 V fed from the outside of the chip and usually used for the reading operation), and an erase voltage (e.g., at -7 V) having a polarity opposed to that of the aforementioned Vcc power source is applied to the control gate electrode of each memory cell and is fed from a voltage converter (or booster) in the aforementioned nonvolatile semiconductor memory device. According to this construction, it is possible to unify the power supply voltage to 5 V and to reduce the erasure unit. For the batch erasing operation, the source to transmit a high leakage current is directly driven by the Vcc power source, and the control gate for establishing a high electric field between itself and the source is fed with an erase voltage having a polarity opposed to that of the Vcc power source. As a result, what flows through the control gate is a fine tunnel current which makes a direct contribution to the erasure so that the control gate can be driven by a booster circuit disposed in the nonvolatile semiconductor memory device. Thus, the chip batch erasing operation by the single Vcc power source can be realized without sacrificing the erasing rate. As compared with the erasing operation which is effected by applying a Vss voltage (e.g., at 0 V) to the control gate and a Vpp voltage (e.g., at 12 V) to the source, the source voltage can be lowered from the Vpp voltage to the Vcc voltage. As a result, it is possible to suppress remarkably the phenomenon that the positive holes established inter-band tunnel are changed into hot holes between the source and the substrate and injected into and trapped by the gate oxide film. Moreover, the erasing system, in which a high voltage is applied to the source, can erase only a relatively large block unit of 16 Kbytes, for example, in which the source lines are shared for high integration. In the negative voltage erasing system, on the contrary, the erasure can be effected at a word line unit. Since, moreover, the memory cells connected with a common word line never fails to be erased altogether, the time period for the program disturb (i.e., the phenomenon that the memory cells have their threshold voltages changed in the partially selected state of the word lines for applying the program voltage only to the control gates of the memory cells) to be experienced by the individual cells may be thought to a sum of the time periods necessary for programming the other memory cells on the same word line, so that the phenomenon that the disturb time period will increase in dependence upon the number of times for reprogramming the memory cells can be avoided to provide an excellent endurance for the reprogramming.
In the aforementioned Japanese Patent Laid-Open No. 219496/1991, there is further disclosed a structure in which circuits for selectively outputting the negative voltage Vppn necessary for the erasure and the voltages Vcc, Vpp and Vss are arranged between an address buffer and the word lines. This circuit is constructed, as shown in FIG. 11, by connecting the sources of N-channel type MOSFET Q100 and Q101 for a final stage inverter circuit INV100 and a preceding inverter circuit INV200 with the negative voltage Vppn at the erasing time.